1. Field of the Invention
The present invention relates to a semiconductor module including a MOS (metal-oxide semiconductor) type solid-state image pickup device, a MOS type solid-state image pickup device, a camera and a method of manufacturing a camera.
2. Description of the Related Art
So far a MOS camera module, for example, is known as a semiconductor module including a MOS type solid-state image pickup device. In order to manufacture a small MOS camera module, there is a promising method of overlaying a MOS type solid-state image pickup device (hereinafter referred to as an “MOS image sensor chip”) and a signal processing chip with each other.
As a MOS camera module according to the related-art example 1, there is known a SIP (system in package) arrangement which is described in a non-patent reference 1, for example. In this MOS camera module, a MOS image sensor chip is overlaid over and bonded to a signal processing chip, the MOS image sensor chip and the signal processing chip are disposed on a circuit board, the two chips and the circuit board are treated by a wire bonding process and then the MOS image sensor chip and the signal processing chip are interconnected with each other by this wiring bonding process.
FIG. 1 of the accompanying drawings is a schematic diagram showing an arrangement of a MOS image sensor chip according to the related art. As shown in FIG. 1, this MOS image sensor chip 1 includes a pixel portion 2 in which a plurality of pixels 3 is arrayed in a two-dimensional fashion (that is, an XY matrix fashion), a column portion 4, an output circuit 6 connected to a horizontal signal line 5, a vertical driving circuit 7, a horizontal driving circuit 8 and a control circuit 9.
The control circuit 9 is supplied with an input clock and data for instructing operation modes from the outside of the MOS image sensor 1. In response to these input clock and data, the control circuit 9 supplies clocks and pulses to the following respective portions so that the respective portions may become to operate.
The vertical driving circuit 7 selects a row of the pixel portion 2 and a necessary pulse is supplied to the pixels of the selected row through a control wiring extended in the lateral direction, although not shown.
The column portion 4 has column signal processing circuits arrayed corresponding to the columns. The column signal processing circuit 10 is supplied with a pixel signal of one line amount and processes the thus supplied signal in a suitable processing fashion such as a CDS (Correlated Double Sampling: processing for eliminating a fixed pattern noise), a signal amplification and an A/D (analog-to-digital) conversion.
The horizontal driving circuit 8 selects the column signal processing circuits 10 sequentially and supplies signals of the column signal processing circuits 10 to the horizontal signal line 5. The output circuit 6 processes the signal from the horizontal line 5 and outputs the thus processed signal. For example, the processing done by the output circuit 6 may be a variety of processing such as only buffering or black level adjustment, correction of column scattering, signal amplification, color processing prior to the buffering.
FIG. 2 is a circuit diagram showing an example of a pixel circuit in the MOS image sensor 1 shown in FIG. 1. In this example, four pixels constitute one cell.
As shown in FIG. 2, this pixel circuit includes four photodiodes PD [PD1, PD2, PD3, PD4] serving as photoelectric-converting elements. The photodiodes PD1 to PD4 are connected to corresponding four transfer transistors 12 [121, 122, 123, 124], respectively. Transfer wirings 161 to 164 are connected to the gates of the respective transfer transistors 121 to 124. The drains of the respective transfer transistors 121 to 124 are connected to be common, which is then connected to the source of a reset transistor 13. A so-called floating diffusion FD between the drain of the transfer transistor 12 and the source of a reset transistor 13 is connected to the gate of an amplifying transistor 14. The drain of the reset transistor 13 is connected to a power supply wiring 15 and the gate thereof is connected to a reset wiring 17. Also, there is provided a selection transistor 18 whose drain is connected to the power supply wiring 15. The source of the selection transistor 18 is connected to the drain of the amplifying transistor 14. A selection wiring 19 is connected to the gate of the selection transistor 18. The photodiodes PD [PD1 to PD4], the transfer transistors 12 [121 to 124], the reset transistor 13, the selection transistor 18 and the amplifying transistor 14 constitute one cell which results from collecting four pixels (photodiodes). On the other hand, the source of the amplifying transistor 14 is connected to the vertical signal line 21. A load transistor 22 whose drain is connected to the vertical signal line 21 and which may serve as a constant current source, which will be described later on, is connected to the vertical signal line 21 as a part of the column signal processing circuit 10. A load wiring 23 is connected to the gate of the load transistor 22.
In this pixel circuit, signal electrical charges are photoelectrically converted by the four photodiodes PD [PD1 to PD4]. Photoelectrons (signal electrical charges) of the photodiodes PD are transferred through the corresponding transfer transistors 12 [121 to 124] to the floating diffusion FD. Since the floating diffusion FD is connected to the gate of the amplifying transistor 14, if the selection transistor 18 is turned ON, then a signal corresponding to an electrical potential of the floating diffusion FD is output through the amplifying transistor 14 to the vertical signal line 21.
The reset transistor 13 discards the signal electrical charges (electrons) of the floating diffusion FD to the power supply line 15 to reset signal electrical charges of the floating diffusion FD. Lateral direction wirings 19, 17 and 16 [161 to 164] are made common to the pixels of the same row and are thereby controlled by the vertical driving circuit 7.
The load transistor 22, which serves as a constant current source, is provided at a part of the column signal circuit 10. The load transistor 22 and the amplifying transistor 14 of the selected row constitute a source follower to supply its output to the vertical signal line 21.
As a CMOS (complementary metal-oxide semiconductor) image sensor module according to a related-art example 2, there is known such one which is described in a cited non-patent reference 2. In this example, an image sensor chip has a substrate through which wirings are passed and the image sensor is connected to a lower-side chip by using micro bumps. According to this method, because the number of bumps can be increased and an inductance and a capacitor component can be decreased, a high-speed interface becomes possible. Further, the image sensor chip is directly connected to the lower-side chip through the wirings from the pixel portion, whereby simultaneity within the picture can also be obtained.    [Non-patent reference 1]: Sharp technical journal Volume 81, 2001, December, page 34    [Non-patent reference 2]: IEDM 99, pp. 879-882